1. Field of the Invention
This invention relates generally to high speed signaling of data, control and address signals between multiple integrated circuits on a bus or point to point with reduced power consumption. Various output driver and terminating schemes are described. Also, a clocking scheme for using a signaling technique for bus applications is described.
2. Description of the Background Art
Semiconductor integrated circuits used in digital computing and other digital applications often use a plurality of Very Large Scale Integration (VLSI) interconnected circuits for implementing binary communication across single or multi-segmented transmission lines. Conventional transmission lines include traces, which are formed on a suitable substrate, such as a printed circuit board. Each transmission line may be designed, for example, using so-called micro-strip traces and strip line traces to form a transmission line having a characteristic impedance on the order of about 50-70 ohms. Alternatively, each transmission line may have its opposite ends terminated in their characteristic impedance. The output load on a driver for such a transmission line may be as low as 25-35 ohms.
To consume reasonable power, high frequency signaling requires small amplitude signals. For a receiver to detect voltage swings (e.g., 0.8 v to 1.2 v) easily in a noisy environment like GTL, HSTL, SSTL or RAMBUS, the current must also be very large (e.g., on the order of 50 to 60 milliamps per driver). A typical receiver uses a comparator with a voltage reference (VREF) signal configured midway between a high input voltage (VIH) and a low input voltage (VIL). The VREF signal is a high impedance DC voltage reference which tracks loosely with power supplies over time, but cannot respond to instantaneous noise. Conventionally, High Output Voltage (VOH) and Low Output Voltage (VOL) denote signals emerging from the transmitting source, and VIL and VIH denote signals arriving at the input of the receiving device, although they can be considered the same signal.
FIG. 1A is a block diagram illustrating a prior art receiver 10 using RAMBUS technology. The system 10 includes a pad 100 coupled via signal lines 103 to internal input receivers 110. A VREF signal 105 is coupled to each internal receiver 110. VREF is typically generated from the power supply (not shown). Usually, the DC value of the power supply varies by five percent (5%). FIG. 1B is a timing diagram 125 illustrating an example signal relative to a high reference voltage (VREFh) and a low reference voltage (VREFl). The VREFh and VREFl values typically depend on power supply variation used to generate the VREF signal. The large voltage swing, i.e., the difference between a high voltage signal (VIH) and a low voltage signal (VIL), and stable signal levels above and below the VREF signal are required for reliable detection of signal polarity. The voltage swing of current single-ended signaling technologies is conventionally around 0.8 v.
FIG. 1C is a block diagram illustrating schematics of a prior art receiver 150 using RAMBUS technology. The receiver 150 samples the level of input signal 167 and of the VREF signal 154 until the signal reaches a stable level, at which time the pass gates 160 and 165 turn off. Once the pass gates 160 and 165 turn off, the sense gate 172 is enabled to eliminate current injection. FIG. 1D is a timing diagram 175 illustrating operation of the receiver 150 for an example signal. The receiver 150 samples the input reference and input signal until the signal reaches a stable level, e.g., a low logic level (VIL), and, while the input signal is stable, the receiver 150 senses the value of the input signal. As stated above, for reliable signal detection, the signal voltage swing must be fast enough to allow all the receivers 150 to sample a stable signal with an adequate margin for set-up and hold time. This voltage swing should occur in less than 30% of the minimum cycle time to allow margin for signal skew, set-up and hold-times. As the minimum cycle time reduces below 1 nanosecond, the margins reduce for signal skew, set-up time and hold-time, with the additional burden on the driver current in a high capacitance loading environment operating at high frequency. Low voltage differential signaling (LVDS) used by IEEE P1596.3 can overcome these problems by using a 250 mv voltage swing at the expense of running complementary signals. Running complementary signals inevitably increases the pin count and package size.
Further, computer systems typically utilize a bus system in which several devices are coupled to the bus. Most of them use a clock to validate data, address and control signals. FIG. 21 illustrates a prior art system 2100 for DRDRAM, which uses a clock line 2130 having two segments 2136 and 2138. One segment 2136 extends from one end of the data bus to a turnaround point 2137 near the second end of the bus. The other clock segment 2138 extends from the turnaround 2137 back to the first end of the data bus. The signal bus 2120 carries data, address and control signals. This topology ensures that a signal sent on the bus 2120 always travels contemporaneously with and in the same direction as the clock 2132 used by the device to receive the signal. This works fine if the loading of all signals and the clock is almost identical and the clock 2132 is used to sample and receive the signal. However, sometimes the system might require twice the data bandwidth in which case this type of bus system 2100 needs to double the number of signals even though the address and control signals are identical, and could have been shared.
Accordingly, there is a need for low power drivers and reliable receivers for high frequency operation of a large number of single-ended signals in existing technology for low cost VLSI digital systems.
A system uses small swing differential source synchronous voltage and timing reference signals (SSVTR and /SSVTR) to compare single-ended signals of the same swing generated from the same integrated circuit for high frequency signaling. It will be appreciated that xe2x80x9c/xe2x80x9d is being used to indicate a logical NOT. All signals are terminated with their characteristic impedance on both ends of the transmission lines. SSVTR and /SSVTR toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled, optionally by using exclusive-OR logic with SSVTR and /SSVTR. Until SSVTR and /SSVTR have changed their binary value, the coupled comparator in the receiver detects whether a change in signal binary value occurred. Again, it will be appreciated that SSVTR and /SSVTR change their binary value every time the signal can change its binary value. SSVTR and /SSVTR are preferably synchronized with the signal.
The method includes the steps of obtaining an oscillating source synchronous voltage and timing reference and its complement (SSVTR and /SSVTR), and receiving an incoming single-ended signal. The method compares the oscillating reference against the incoming signal by a first comparator to generate a first result, and compares the complement against the incoming signal by a second comparator to generate a second result. The method then selects one of the first result or the second result as an output signal based on the previous signal. The step of selecting one of the results includes comparing the output signal to the reference (SSVTR) and to the complement (/SSVTR). The step of selecting further includes manipulating the output signal from the previous signal towards the first result or second result, based on the comparator which is currently coupled. If the incoming signal changes, the step of selecting includes maintaining the same comparator coupled. If the incoming signal stays the same, the step of selecting includes de-coupling the currently coupled comparator and coupling the other comparator. The method then allows the circuit to stabilize.
The system and method advantageously eliminate the need for a high impedance VREF signal for comparison of small swing single-ended signals. This reduces the need for three distinct voltage levels (the output high level, output low level and the VREF level) to two distinct voltage levels (the output high level and the output low level). Eliminating VREF reduces necessary voltage swing and accordingly reduces power consumption. Using a receiver with dual comparators allows coupling of the receiver to the same comparator when the signal changes every cycle. Only one comparator is coupled based on the current binary value of the signal and SSVTR. The system has an individually adjustable delay for each receiver to couple or de- couple the comparator, thereby reducing the effect of skew during transmission of source synchronous signals. The system may have multiple differential source synchronous voltage and timing reference signals to compare multiple single-ended signals in the same integrated circuit such as a microprocessor or system controller that has many signals. The system and method provide differential signaling benefits in a single-ended signaling system.
Using the same concept, the system may have bi-directional complementary source synchronous voltage and timing reference signals to compare bi-directional single-ended signals. The system may have a driver or transmitter for controlling the signal slew rate to be a substantial portion the total signal period, thereby reducing output current. The system may have internal impedance matching circuitry such as pull-up resistors or grounded gate p-channel for matching the characteristic impedance of the transmission line on both ends of a point-to-point connection between CPU and cache or CPU and system controller. The system has a dual comparator circuit to convert a single-ended bus with two complementary signals to be transmitted and received with comparable noise immunity of differential bus for internal data bus of memory, processor or other wide data bus type integrated circuits. The system preferably has variable device size of the transmitter with slow turning-on and slow turning-off to have similar slew rates for all signals in each group of SSVTR and /SSVTR and plurality of signals which are transmitted together. Further, it will be appreciated that the control signals and address signals may be transmitted on a different channel than the data signals. This enables running the control and address channel at a different frequency than the data channel, and enables different loads to be applied to each of the channels.
A system of the present invention for optimizing communication with a master device includes a master device for transmitting master device requests; a plurality of slave devices coupled to the master device, each slave device for performing an operation based on a master device request; first clock generator logic coupled to the slave device for generating a first clock signal to control signal transfer between the slave devices and the master device, the maximum signal flight time between the slave devices and the master device being greater than the cycle time of the first clock signal; and second clock generator logic coupled to the slave device for generating a second clock signal to trigger each slave device to initiate the operation, the maximum signal flight time between the slave devices and the master device being less than half of the cycle time of the second clock signal.